1. Field of the Invention
The present invention relates to data communication devices that are communication tools, such as readers-writers, each having an antenna driven by a semiconductor circuit including a combination of metal oxide semiconductor (MOS) transistors. More particularly, the present invention relates to a data communication device configured to prevent latchup in a semiconductor circuit based on an external magnetic field received by an antenna.
2. Description of the Related Art
Non-contact integrated circuit (IC) cards for wireless data communication have been utilized in various fields in recent years. IC cards, which are devices each including a central processing unit (CPU) functioning as data processing means, a memory functioning as data storage means, and data communication means, are applied to various fields. For example, ticket information or season-ticket information is stored in a memory in an IC card and the stored information is read by using a reader-writer installed at a ticket gate in a station to perform ticket-gate control based on the read information. Alternatively, an IC card is used as electronic money for electronic settlement or is used as a cash card, an employee identification (ID) card, or an ID card including a club card.
Reading information from an IC card or writing information in the IC card is performed via communication with external equipment, such as a reader-writer, that is capable of communicating with the IC card. However, since the IC card itself has no power supply provided therein, it operates with electric power externally supplied. Specifically, an IC card is structured such that electromagnetic waves supplied from a reader-writer, which is external equipment, are received by an antenna provided in the IC card, a voltage generated at both ends of the antenna is rectified, and the rectified voltage is supplied to circuits in the IC card as electric power.
Basically, in an IC card, carrier waves supplied from an external reader-writer are rectified to provide a direct-current power supply that is used as a driving power supply for internal circuits including a processor and a memory. Even if an IC card is incorporated in a device, such as a portable device, having a power supply, the IC card cannot use the power supply of the device. However, integrating a reader-writer function with an IC card function on a single semiconductor chip can reduce the mounted area. This integration is advantageous to mount in a small device, such as a cellular phone, and such an IC module having the integrated functions is in widespread use. Connecting an antenna for the reader-writer and an antenna for the IC card to the input and output terminals of the IC module enables non-contact communication with an external IC card or an external reader-writer.
In order to mount an IC module having the reader-writer function and the IC card function integrated therein in devices, such as portable devices, required for being downsized, two antennas for the reader-writer and the IC card are adjacently provided or a common antenna is shared between the reader-writer and the IC card to improve the space utilization and reduce the cost. Such a circuit configuration is disclosed in, for example, Japanese Unexamined Patent Application Publication No. 11-213111.
However, when electromagnetic waves supplied from an external device, such as a reader-writer, are received by the adjacent antennas (or common antenna) for supplying electric power to the IC card function, so-called latchup disadvantageously occurs. Latchup is a phenomenon in which a current continues to flow through a semiconductor device in the reader-writer because electric signals caused by the electromagnetic waves are supplied to a transmitting circuit in the reader-writer. This is a problem caused by the configuration of a complementary metal oxide semiconductor (CMOS) used as the semiconductor circuit in the reader-writer.
FIG. 1 is a diagram illustrating the effect of reception of external electromagnetic waves in an IC module 110. Referring to FIG. 1, the IC module 110 includes an IC card circuit 111, a reader-writer transmitter circuit 112, and a reader-writer receiver circuit 113. When an IC-card antenna 121 is provided adjacent to a transmitting and receiving antenna 122 for a reader-writer or the IC-card antenna 121 and the transmitting and receiving antenna 122 for the reader-writer are structured as one antenna, electromagnetic waves supplied from an external reader-writer 130 are received in both the IC-card antenna 121 and the transmitting and receiving antenna 122 for the reader-writer. As a result, electric signals caused by the electromagnetic waves are supplied to the reader-writer transmitter circuit 112 causing the latchup in the circuit, having the CMOS configuration, for the reader-writer.
As described above, latchup is a phenomenon caused by the configuration of a CMOS used as a semiconductor integrated circuit.
FIG. 2 shows an exemplary circuit configuration of a reader-writer having a CMOS configuration. Referring to FIG. 2, the output ports of CMOSs 210 and 220 are connected to the respective ends of an antenna 200 through the corresponding capacitors. The CMOSs 210 and 220 each have a configuration in which the drain D of an N-channel MOS transistor (NMOS) having electron carriers is connected to the drain D of a P-channel MOS transistor (PMOS) having hole carriers.
In the NMOS, when a gate G has a voltage higher than that of a source S (when the gate G is positive with respect to the source S), an N-type channel is formed between the source S and drain D and the resistance between the source S and drain D is decreased. This corresponds to switching-on. When the gate G has a voltage lower than that of the source S (when the gate G is negative with respect to the source S), no channel is formed and the resistance between the source S and drain D is increased. This corresponds to switching-off. In contrast, in the PMOS, when the gate G has a voltage lower than that of the source S (when the gate G is negative with respect to the source S), a P-type channel is formed between the source S and drain D and the transistor switches on. When the gate G has a voltage higher than that of the source S (when the gate G is positive with respect to the source S), no channel is formed and the transistor switches off.
A signal output through the antenna 200 is set with an output Out1 from the CMOS 210 and an output Out2 from the CMOS 220. An input signal In1 is supplied to the CMOS 210 from a signal supplier (not shown) and an input signal In2 is supplied to the CMOS 220 from the signal supplier. The input signal In1 supplied to the CMOS 210 is a signal inverted by an inverter 230.
For example, when an input signal In1 having a GND level is supplied to the CMOS 210, a PMOS 211 turns on and an NMOS 212 turns off. A signal having a VDD level is output from the CMOS 210 (Out1). Concurrently, an input signal In2 having the VDD level is supplied to the CMOS 220 to turn off a PMOS 221 and to turn on an NMOS 222. A signal having the GND level is output from the CMOS 220 (Out2).
In contrast, when an input signal In1 having the VDD level is supplied to the CMOS 210, the PMOS 211 turns off and the NMOS 212 turns on. A signal having the GND level is output from the CMOS 210 (Out1). Concurrently, an input signal In2 having the GND level is supplied to the CMOS 220 to turn on the PMOS 221 and to turn off the NMOS 222. A signal having the VDD level is output from the CMOS 220 (Out2).
These two output states are sequentially set based on the input signal. A current is generated at a coil functioning as the antenna 200 based on the output Out1 from the CMOS 210 and the output Out2 from the CMOS 220, and an electromagnetic wave corresponding to the input signal is output. The output electromagnetic wave is received by an antenna of an external device, such as an external reader-writer, and the received signal is transmitted.
FIG. 3 is a cross-sectional view of a typical CMOS configuration. The CMOS configuration in FIG. 3 includes a PMOS consisting of an N area (Nwell) 251 on a P-type substrate (Psub) 250 and an NMOS consisting of a P area (Pwell) 252 on the P-type substrate (Psub) 250. Although the P-type substrate (Psub) 250 is shown as distinct from the P area (Pwell) 252 in FIG. 3, the P-type substrate (Psub) 250 and the P area (Pwell) 252 may be set as one area having the identical configuration. The configuration shown in FIG. 3 corresponds to the cross section of the CMOS 210 or the CMOS 220 shown in FIG. 2.
The CMOS includes the N-channel MOS transistor (NMOS) having electron carriers and the P-channel MOS transistor (PMOS) having hole carriers.
As described above, in the NMOS, when the gate G has a voltage higher than that of the source S (when the gate G is positive with respect to the source S), an N-type channel is formed between the source S and drain D and the resistance between the source S and drain D is decreased. This corresponds to switching-on. When the gate G has a voltage lower than that of the source S (when the gate G is negative with respect to the source S), no channel is formed and the resistance between the source S and drain D is increased. This corresponds to switching-off. In contrast, in the PMOS, when the gate G has a voltage lower than that of the source S (when the gate G is negative with respect to the source S), a P-type channel is formed between the source S and drain b and the transistor switches on. When the gate G has a voltage higher than that of the source S (when the gate G is positive with respect to the source S), no channel is formed and the transistor switches off.
As shown by broken lines in FIG. 3, the source and drain electrodes of the PMOS and those of the NMOS have a PN junction structure, and PN-junction diodes are formed in these four electrodes. The PN-junction diode, which is necessarily structured in the MOS, is called a parasitic diode.
Based on this parasitic diode, the CMOS has a circuit configuration including three transistors, that is, a PNP transistor (A), an NPN transistor (B), and a PNP transistor (C), as shown in FIG. 3. It is supposed that latchup is caused in a circuit that is formed based on the parasitic diode.
A sequence whereby latchup occurs will now be described. It is supposed that latchup occurs through the following states from (1) to (6).
(1) When an electrical signal is generated by an external electromagnetic wave in an output part, a forward current flows from a P area 261 of the drain D to the N area (Nwell) 251 in the PMOS.
(2) As a result, the PNP transistor (A) based on the parasitic diode in the N area (Nwell) 251 switches on.
(3) When the PNP transistor (A) switches on, a current flows into the P area (Pwell) 252 (=P-type substrate (Psub) 250) through the PNP transistor (A) to increase the voltages of the P area (Pwell) 252 and the P-type substrate (Psub) 250.
(4) As a result, the NPN transistor (B) based on the parasitic diode in the P area (Pwell) 252 switches on.
(5) When the NPN transistor (B) switches on, a current flows from the N area (Nwell) 251 to the P area (Pwell) 252 (=P-type substrate (Psub) 250) through the NPN transistor (B) to decrease the voltage of the N area (Nwell) 251.
(6) The PNP transistor (C) based on the parasitic diode in the N area (Nwell) 251 switches on along with the reduction in voltage of the N area (Nwell) 251. As a result, a current supplied from a power supply VDD flows from the N area (Nwell) 251 to the P area (Pwell) 252 (=P-type substrate (Psub) 250) through the PNP transistor (C) to increase the voltage of the P area (Pwell) 252 (=P-type substrate (Psub) 250).
The state (6) is equal to the state (3). The change of states in the order of (6)→(3)→(4)→(5)→(6)→(3)→(4) . . . is continuously repeated, so that a current continues to flow through the CMOS configuration in a reader-writer. As a result, power is consumed in a power supply, for example, in a battery and devices are deteriorated. Furthermore, a normal signal output provided when the CMOS functions as a reader-writer is undesirably inhibited.